1. Scope

1.1 This guide defines the requirements and procedures for testing integrated circuits and other devices for the effects of single event phenomena (SEP) induced by irradiation with heavy ions having an atomic number Z > 2. This description specifically excludes the effects of neutrons, protons, and other lighter particles that may induce SEP via another mechanism. SEP includes any manifestation of upset induced by a single ion strike, including soft errors (one or more simultaneous reversible bit flips), hard errors (irreversible bit flips), latchup (permanent high conducting state), transients induced in combinatorial devices which may introduce a soft error in nearby circuits, power field effect transistor (FET) burn-out and gate rupture. This test may be considered to be destructive because it often involves the removal of device lids prior to irradiation. Bit flips are usually associated with digital devices and latchup is usually confined to bulk complementary metal oxide semiconductor, (CMOS) devices, but heavy ion induced SEP is also observed in combinatorial logic programmable read only memory, (PROMs), and certain linear devices that may respond to a heavy ion induced charge transient. Power transitors may be tested by the procedure called out in Method 1080 of MIL STD 750.

1.2 The procedures described here can be used to simulate and predict SEP arising from the natural space environment, including galactic cosmic rays, planetary trapped ions and solar flares. The techniques do not, however, simulate heavy ion beam effects proposed for military programs. The end product of the test is a plot of the SEP cross section (the number of upsets per unit fluence) as a function of ion LET (linear energy transfer, or ionization deposited along the ion's path through the semiconductor). This data can be combined with the system's heavy ion environment to estimate a system upset rate.

1.3 Although protons can cause SEP, they are not included in this guide. A separate guide addressing proton induced SEP is being considered.

1.4 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this guide.

1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

2. Referenced Documents (purchase separately) The documents listed below are referenced within the subject standard but are not provided as part of the standard.

Military Standard

Keywords

SEB; SEE; SEFI; SEGR; SEL; SEP; SEP cross section; SEU; single event; single event effect; single event phenomena; single event upset; space environment: Destructive testing--semiconductors; Dosimetry; Electrical conductors (semiconductors); Electron radiation; Failure end point--electronic components/devices; Fluence; Galactic cosmic rays; Germanium--semiconductor applications; Integrated circuits; Ionizing radiation; Irradiance/irradiation--semiconductors; Linear energy transfer (LET); Radiation exposure--electronic components/devices; Silicon semiconductors; Single crystal silicon semiconductors; Single-event phenomenon (SEP); Solar flares; Upset threshold;

ICS Code

ICS Number Code 31.080.01 (Semi-conductor devices in general)

DOI: 10.1520/F1192-00

ASTM International is a member of CrossRef.