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eLibrary > BS EN 62271-101:2013+A1:2018 High-voltage switchgear and controlgear - Synthetic testing >

BS EN 62271-101:2013+A1:2018 High-voltage switchgear and controlgear - Synthetic testing, 2018

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BS EN 62271-101:2013+A1:2018 High-voltage switchgear and controlgear - Synthetic testing, 2018

National foreword
CONTENTS
FOREWORD
1 Scope
2 Normative references
3 Terms and definitions
4 Synthetic testing techniques and methods for short-circuit breaking tests [Go to Page]
4.1 Basic principles and general requirements for synthetic breaking test methods [Go to Page]
4.1.1 General
4.1.2 High-current interval
4.1.3 Interaction interval
4.1.4 High-voltage interval
4.2 Synthetic test circuits and related specific requirements for breaking tests [Go to Page]
4.2.1 Current injection methods
4.2.2 Voltage injection method
4.2.3 Duplicate circuit method (transformer or Skeats circuit)
4.2.4 Other synthetic test methods
4.3 Three-phase synthetic test methods
Table 1 – Test circuits for test duties T100s and T100a
Table 2 – Test parameters during three-phase interruption for test-duties T10, T30, T60 and T100s, kpp = 1,5
Table 3 – Test parameters during three-phase interruption for test-duties T10, T30, T60 and T100s, kpp = 1,3
Table 4 – Test parameters during three phase interruption for test-duties T10, T30, T60 and T100s, kpp = 1,2
5 Synthetic testing techniques and methods for short-circuit making tests [Go to Page]
5.1 Basic principles and general requirements for synthetic making test methods [Go to Page]
5.1.1 General
5.1.2 High-voltage interval
5.1.3 Pre-arcing interval
5.1.4 Latching interval and fully closed position
5.2 Synthetic test circuit and related specific requirements for making tests [Go to Page]
5.2.1 General
5.2.2 Test circuit
5.2.3 Specific requirements
6 Specific requirements for synthetic tests for making and breaking performance related to the requirements of 6.102 through 6.111 of IEC 62271-100:2008 [Go to Page]
Table 5 – Synthetic test methods for test duties T10, T30, T60, T100s, T100a, SP, DEF, OP and SLF
Figures [Go to Page]
Figure 1 – Interrupting process – Basic time intervals
Tables [Go to Page]
Figure 2 – Examples of evaluation of recovery voltage
Figure 3 – Equivalent surge impedance of the voltage circuit for the current injection method
Figure 4 – Making process – Basic time intervals
Figure 5 – Typical synthetic making circuit for single-phase tests
Figure 6 – Typical synthetic making circuit for out-of-phase
Figure 7 – Typical synthetic make circuit for three-phase tests (kpp = 1,5)
Figure 8 – Comparison of arcing time settings during three-phase direct tests (left) and three-phase synthetic (right) for T100s with kpp = 1,5
Figure 9 – Comparison of arcing time settings during three-phase direct tests (left) and three-phase synthetic (right) for T100a with kpp = 1,5
Annex A (informative) Current distortion [Go to Page]
Figure A.1 – Direct circuit, simplified diagram
Figure A.2 – Prospective short-circuit current
Figure A.3 – Distortion current
Figure A.4 – Distortion current
Figure A.5 – Simplified circuit diagram
Figure A.6 – Current and arc voltage characteristics for symmetrical current
Figure A.7 – Current and arc voltage characteristics for asymmetrical current
Figure A.8 – Reduction of amplitude and duration of final current loop of arcing
Figure A.9 – Reduction of amplitude and duration of final current loop of arcing
Figure A.10 – Reduction of amplitude and duration of final current loop of arcing
Figure A.11 – Reduction of amplitude and duration of final current loop of arcing
Annex B (informative) Current injection methods [Go to Page]
Figure B.1 – Typical current injection circuit with voltage circuit in parallel with the test circuit-breaker
Figure B.2 – Injection timing for current injection scheme with circuit B.1
Figure B.3 – Examples of the determination of the interval of significant change of arc voltage from the oscillograms
Annex C (informative) Voltage injection methods [Go to Page]
Figure C.1 – Typical voltage injection circuit diagram with voltage circuit in parallel with the auxiliary circuit-breaker (simplified diagram)
Figure C.2 – TRV waveshapes in a voltage injection circuit with the voltage circuit in parallel with the auxiliary circuit-breaker
Annex D (informative) Skeats or duplicate transformer circuit [Go to Page]
Figure D.1 – Transformer or Skeats circuit
Figure D.2 – Triggered transformer or Skeats circuit
Annex E (normative) Information to be given and results to be recorded for synthetic tests
Annex F (normative) Synthetic test methods for circuit-breakerswith opening resistors [Go to Page]
Figure F.1 – Test circuit to verify thermal re-ignition behaviour of the main interrupter
Figure F.2 – Test circuit to verify dielectric re-ignition behaviour of the main interrupter
Figure F.3 – Test circuit on the resistor interrupter
Figure F.4 – Example of test circuit for capacitive current switching tests on the main interrupter
Figure F.5 – Example of test circuit for capacitive current switching tests on the resistor interrupter
Annex G (informative) Synthetic methods for capacitive-current switching [Go to Page]
Figure G.1 – Capacitive current circuits (parallel mode)
Figure G.2 – Current injection circuit
Figure G.3 – LC oscillating circuit
Figure G.4 – Inductive current circuit in parallel with LC oscillating circuit
Figure G.5 – Current injection circuit, normal recovery voltage applied to both terminals of the circuit-breaker
Figure G.6 – Synthetic test circuit (series circuit), normal recovery voltage applied to both sides of the test circuit breaker
Figure G.7 – Current injection circuit, recovery voltage applied to both sides of the circuit-breaker
Figure G.8 – Making test circuit
Figure G.9 – Inrush making current test circuit
Annex H (informative) Re-ignition methods to prolong arcing [Go to Page]
Figure H.1 – Typical re-ignition circuit diagram for prolonging arc-duration
Figure H.2 – Combined Skeats and current injection circuits
Figure H.3 – Typical waveforms obtained during an asymmetrical test using the circuit in Figure H.2
Annex I (normative) Reduction in di/dt and TRV for test duty T100a [Go to Page]
Table I.1 – Last loop di/dt reduction for 50 Hz for kpp = 1,3 and 1,5
Table I.2 – Last loop di/dt reduction for 50 Hz for kpp = 1,2
Table I.3 – Last loop di/dt reduction for 60 Hz for kpp = 1,3 and 1,5
Table I.4 – Last loop di/dt reduction for 60 Hz for kpp = 1,2
Table I.5 – Corrected TRV values for the first pole-to-clear for kpp = 1,3 and fr = 50 Hz
Table I.6 – Corrected TRV values for the first pole-to-clear for kpp = 1,3 and fr = 60 Hz
Table I.7 – Corrected TRV values for the first pole-to-clear for kpp = 1,5 and fr = 50 Hz
Table I.8 – Corrected TRV values for the first pole-to-clear for kpp = 1,5 and fr = 60 Hz
Table I.9 – Corrected TRV values for the first pole-to-clear for kpp = 1,2 and fr = 50 Hz
Table I.10 – Corrected TRV values for the first pole-to-clear for kpp = 1,2 and fr = 60 Hz
Annex J (informative) Three-phase synthetic test circuits [Go to Page]
Figure J.1 – Three-phase synthetic combined circuit
Figure J.2 – Waveshapes of currents, phase-to-ground and phase-to phase voltages during a three-phase synthetic test (T100s; kpp = 1,5 ) performed according to the three-phase synthetic combined circuit
Figure J.3 – Three-phase synthetic circuit with injection in all phases for kpp = 1,5
Figure J.4 – Waveshapes of currents and phase-to-ground voltages during a three-phase synthetic test (T100s; kpp =1,5) performed according to the three-phase synthetic circuit with injection in all phases
Figure J.5 – Three-phase synthetic circuit for terminal fault tests with kpp = 1,3 (current injection method)
Figure J.6 – Waveshapes of currents, phase-to-ground and phase-to-phase voltages during a three-phase synthetic test (T100s; kpp =1,3 ) performed according to the three-phase synthetic circuit shown in Figure J.5
Figure J.7 – TRV voltages waveshapes of the test circuit described in Figure J.5
Annex K (normative) Test procedure using a three-phase current circuit and one voltage circuit [Go to Page]
Table K.1 – Demonstration of arcing times for kpp = 1,5
Table K.2 – Alternative demonstration of arcing times for kpp = 1,5
Table K.3 – Demonstration of arcing times for kpp = 1,3
Table K.4 – Alternative demonstration of arcing times for kpp = 1,3
Table K.5 – Demonstration of arcing times for kpp = 1,5
Table K.6 – Alternative demonstration of arcing times for kpp = 1,5
Table K.7 – Demonstration of arcing times for kpp = 1,3
Table K.8 – Alternative demonstration of arcing times for kpp = 1,3
Table K.9 – Procedure for combining kpp = 1,5 and 1,3 during test-duties T10, T30, T60 and T100s(b)
Table K.10 – Procedure for combining kpp = 1,5 and 1,3 during test-duty T100a
Figure K.1 – Example of a three-phase current circuit with single-phase synthetic injection
Figure K.2 – Representation of the testing conditions of Table K.1
Figure K.3 – Representation of the testing conditions of Table K.2
Figure K.4 – Representation of the testing conditions of Table K.3
Figure K.5 – Representation of the testing conditions of Table K.4
Figure K.6 – Representation of the testing conditions of Table K.5
Figure K.7 – Representation of the testing conditions of Table K.6
Figure K.8 – Representation of the testing conditions of Table K.7
Figure K.9 – Representation of the testing conditions of Table K.8
Annex L (normative) Splitting of test duties in test series taking into account the associated TRV for each pole-to-clear [Go to Page]
Table L.1 – Test procedure for kpp = 1,5
Table L.2 – Test procedure for kpp = 1,3
Table L.3 – Simplified test procedure for kpp = 1,3
Table L.4 – Test procedure for kpp = 1,2
Table L.5 – Simplified test procedure for kpp = 1,2
Table L.6 – Test procedure for asymmetrical currents in the case of kpp = 1,5
Table L.7 – Test procedure for asymmetrical currents in the case of kpp = 1,3
Table L.8 – Test procedure for asymmetrical currents in the case of kpp = 1,2
Figure L.1 – Graphical representation of the test shown in Table L.6
Figure L.2 – Graphical representation of the test shown in Table L.7
Table L.9 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,5 , fr = 50 Hz
Table L.10 – Required test parameters for different asymmetrical conditions in the case of a kpp = 1,3 , fr = 50 Hz
Table L.11 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,2 , fr = 50 Hz
Table L.12 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,5 , fr = 60 Hz
Table L.13 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,3 , fr = 60 Hz
Table L.14 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,2, fr = 60 Hz
Table L.15 – Procedure for combining kpp = 1,5 and 1,3 during test-duties T10, T30, T60 and T100s(b)
Table L.16 – Procedure for combining kpp = 1,5 and 1,3 during test-duty T100a
Annex M (normative) Tolerances on test quantities for type tests [Go to Page]
Table M.1 – Tolerances on test quantities for type tests (1 of 2)
Annex N (informative) Typical test circuits for metal-enclosed and dead tank circuit-breakers [Go to Page]
Figure N.1 – Test circuit for unit testing (circuit-breaker with interaction due to gas circulation)
Figure N.2 – Half-pole testing of a circuit-breaker in test circuit given by Figure N.1 – Example of the required TRVs to be applied between the terminals of the unit(s) under test and between the live parts and the insulated enclosure
Figure N.3 – Synthetic test circuit for unit testing (if unit testing is allowed as per 6.102.4.2 of IEC 62271-100:2008)
Figure N.4 – Half-pole testing of a circuit-breaker in the test circuit of Figure N.3 – Example of the required TRVs to be applied between the terminals of the unit(s) under test and between the live parts and the insulated enclosure
Figure N.5 – Capacitive current injection circuit with enclosure of the circuit-breaker energized
Figure N.6 – Capacitive synthetic circuit using two power-frequency sources and with the enclosure of the circuit-breaker energized
Figure N.7 – Capacitive synthetic current injection circuit – Example of unit testing on half a pole of a circuit-breaker with two units per pole – Enclosure energized with d.c. voltage source
Figure N.8 – Symmetrical synthetic test circuit for out-of-phase switching tests on a complete pole of a circuit-breaker
Figure N.9 – Full pole test with voltage applied to both terminals and the metal enclosure
Annex O (informative) Combination of current injection and voltage injection methods [Go to Page]
Figure O.1 – Example of combined current and voltage injection circuit with application of full test voltage to earth
Figure O.2 – Example of combined current and voltage injection circuit with separated application of test voltage
Bibliography [Go to Page]

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BS EN 62271-101:2013+A1:2018 High-voltage switchgear and controlgear - Synthetic testing, 2018

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